Digital logic can be implemented using several options: discrete logic devices, often called small-scale integrated circuits or SSI, programmable devices such as programmable logic arrays (PLAs) or programmable logic devices (PLDs), masked-programmed gate arrays or cell-based application specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).
FPGAs are general purpose programmable devices that are customized by the end users. FPGAs are composed of an array of configurable logic blocks that are programmably interconnected. The basic device architecture of an FPGA consists of an array of configurable logic blocks (CLBs) embedded in a configurable interconnect structure and surrounded by configurable I/O blocks (IOBs). An IOB allows signals to be driven off-chip or optionally brought onto the FPGA onto interconnect segments. The IOB can typically perform other functions, such as tri-stating outputs and registering incoming or out-going signals. The configurable interconnect structure allows users to implement multi-level logic designs (multi-level refers to logic in which the output signal of one logic unit provides input to another logic unit and the output of that provides input to another, etc.). An FPGA can support hundreds of thousands of gates of logic operating at system speeds of tens of megahertz. The FPGA is programmed by loading programming data into the memory cells controlling the configurable logic blocks, I/O blocks, and interconnect structure.
Each configurable logic block in the FPGA can include configuration memory cells for controlling the function performed by that logic block. These configuration memory cells can implement a lookup table, control multiplexers, and control other logic elements such as XOR gates and AND gates. A lookup table (LUT) stores a truth table which implements that combinational logic function corresponding to the truth table. Each configurable logic block is associated with an adjacent portion of the interconnect structure. The interconnect structure includes programmable interconnect points which control the connection of wiring segments in the programmable interconnect network of the FPGA. Each programmable interconnect point may be a pass transistor controlled by a configuration memory cell. Wire segments on each side of the pass transistor are either connected or not connected depending on whether the transistor is turned on by the corresponding configuration memory cell.
Configuration is the process of loading a stream of bits containing the program data into the configuration memory cells which control the configurable logic blocks and I/O blocks of the FPGA. The bitstream is loaded into the FPGA serially to minimize the number of pins required for configuration and to reduce the complexity of the interface to external memory. The bitstream is broken into packets of data called frames. As each frame is received, it is shifted through a frame register until the frame register is filled. The data in the frame register of the FPGA are then loaded in parallel into one column of configuration memory cells forming the memory array. (The configuration memory cells which control a configurable logic block typically occupy a two dimensional section of the array.) The configuration memory cells make up the lookup tables and control programmable interconnect points, multiplexers, and other programmable elements of a configurable logic block or I/O block. Following the loading of the first frame, subsequent frames of bitstream data are shifted into the FPGA, and another column of configuration memory cells in the array of CLBs is designated to be loaded with a frame of bitstream data.
Because the functions performed by the logic or I/O blocks are determined by the values of the configuration memory cells, any error in the values could affect the functions. In a FPGA configured to implement a complex design, it is possible that a single error could render the design inoperative. Although the memory cells are normally very reliable, there is a concern that they might be disturbed in a high-radiation or high-temperature environment. Consequently, it is desirable to include in the FPGA an error correction and reporting mechanism.